This page describes the test results of the first prototype ExpressCard. The screenshot below shows the 12 MHz clock signal on pin 3 (OSCO) of the FT2232H. The second screenshot of my scope shows the 27 MHz clock signal on pin 11 (Y1) of the CDCE913 clock synthesizer, which is fed as CLK_OSC1 to the FPGA.
Connector CN2 has been soldered onto the first board to enable a verification of the JTAG chain using Xilinx Platform Cable USB II. With power supplied to the 3.3V and 3.3VAUX pins of the ExpressCard connector CN1, the following result of a boundary scan in Impact was obtained:
Since the CN2 header needs to be removed to fit the board in an ExpressCard enclosure, I bought an USB to ExpressCard adapter. This part only takes the narrow part of the ExpressCard/54 board, leaving full access to most of the board for troubleshooting. The adapter is not suitable for ExpressCards using the PCI Express 1x lane, but USB 2.0 and some power is all I need. The operation voltage specification from some other site offering the same product: “3.3V ± 5% directly from USB port, 3.3Vaux and 1.5V power output”. Unfortunately, this turned out to be incorrect after several attempts to connect to the JTAG chain via this adapter and port B of the FT2232H. The ExpressCard adapter does not provide 3.3Vaux and the pins for 1.5V are also not wired on the PCB in this product. A quick measurement on the board showed only 0.9 V for VCCAUX, which is not sufficient for the JTAG part of the chips to function correctly.
With a short white wire, pin 12 (3.3VAUX) is powered by the 3.3V present on pins 14 and 15.
The ExpressCard is detected as FT2232C Dual USB-UART/FIFO IC on first use. The next step is to program the 93LC46B EEPROM with configuration settings for the FT2232H chip.
Unfortunately, the EEPROM programming utility of FTDI (FT_PROG) is only available for Microsoft Windows. Thus, a virtual Windows XP system needs to boot up in VirtualBox and the USB device is passed on. After enumeration of the new device (balloons on the taskbar) is finally completed, the FT_PROG can be started to connect to the EEPROM.
Initially, the EEPROM is reported to be blank. Changing the settings as needed, writing the configuration to the EEPROM and reading the content of the EEPROM back in FT_PROG results in the following screenshot.
The MPSSE mode of the FT2232H is entered by software commands and does not need to be selected in the EEPROM configuration. The hardware configuration of port B will be set to 245 FIFO and used with the D2XX driver. Port A of the FT2232H will be used as UART with the D2XX driver.
Next, let’s try to connect to the JTAG chain using the second port on the FT2232H. The following set of instructions builds the latest version of UrJTAG.
sudo apt-get install autoconf automake bison pkg-config flex
sudo apt-get install libtool libgettextpo-dev libreadline-dev libftdi-dev
wget http://www.ftdichip.com/Drivers/D2XX/Linux/libftd2xx1.1.12.tar.gz
tar xzvf libftd2xx1.1.12.tar.gz
mv release libftd2xx1.1.12
sudo cp libftd2xx1.1.12/build/x86_64/lib* /usr/local/lib64
sudo chmod 0755 /usr/local/lib64/libftd2xx.so.1.1.12
sudo ln -sf /usr/local/lib64/libftd2xx.so.1.1.12 /usr/local/lib64/libftd2xx.so
svn co http://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk urjtag
cd urjtag/urjtag
./autogen.sh
export LIBS="-lpthread -ldl"
export LDFLAGS=-L/usr/local/lib64
./configure --with-ftd2xx="/home/radko/Downloads/libftd2xx1.1.12"
make -j4
sudo make install
For running UrJTAG, the following sequence of commands seems necessary:
sudo rmmod ftdi_sio
sudo rmmod usbserial
sudo LD_LIBRARY_PATH=/usr/local/lib64 /usr/local/bin/jtag
Regular users can have access rights to upload configurations to the USB device with UrJTAG. This right is set by adding a new rule to udev, typically via a separate file (/etc/udev/rules.d/99-urjtag.rules) with following line:
SUBSYSTEM=="usb", ACTION=="add", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="0666", GROUP="plugdev"
A restart of the udev daemon is needed to active the new rule:
sudo service udev restart
The initial output of UrJTAG is a follows:
jtag> bsdl path /home/radko/Projects/documents/ExpressCard_v1.0/bsdl
jtag> bsdl test
-N- Reading file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc2c384_tq144.bsd'
-N- BSDL file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc2c384_tq144.bsd' passed VHDL stage correctly
-N- Got IDCODE: XXXX0110110101011100000010010011
-N- BSDL file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc2c384_tq144.bsd' passed BSDL stage correctly
-N- Reading file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xcf04s_vo20.bsd'
-N- BSDL file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xcf04s_vo20.bsd' passed VHDL stage correctly
-N- Got IDCODE: XXXX0101000001000110000010010011
-N- BSDL file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xcf04s_vo20.bsd' passed BSDL stage correctly
-N- Reading file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc6slx9_tqg144.bsd'
-N- BSDL file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc6slx9_tqg144.bsd' passed VHDL stage correctly
-N- Got IDCODE: XXXX0100000000000001000010010011
-N- BSDL file '/home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc6slx9_tqg144.bsd' passed BSDL stage correctly
jtag> cable ft2232 vid=0x0403 pid=0x6010 interface=1
Connected to libftd2xx driver.
jtag> detect
jtag> idcode 12
Reading 12 bytes of idcode
Read 10010011(0x93) 11000000(0xc0) 11010101(0xd5) 00010110(0x16) 10010011(0x93) 01100000(0x60) 00000100(0x04) 11010101(0xd5) 10010011(0x93) 00010000(0x10) 00000000(0x00) 00100100(0x24)
jtag> discovery
Detecting IR length ... -1
Error: Invalid IR length!
Bug in UrJTAG 0.10 #2039? No. Connecting a logic analyzer to the 14-pin JTAG header and manually changing the state of the 3 output pins (TMS, TDI and TCK) of the FT2232H showed that the TDI line did not change state as commanded. The TDI pin of the chip turned out to have a bad solder connection to the board. The output below was obtained after repairing this:
jtag> bsdl path /home/radko/Projects/documents/ExpressCard_v1.0/bsdl
jtag> cable ft2232 vid=0x0403 pid=0x6010 interface=1
Connected to libftd2xx driver.
jtag> detect
IR length: 22
Chain length: 3
Device Id: 00010110110101011100000010010011 (0x16D5C093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc2c384_tq144.bsd
Device Id: 11010101000001000110000010010011 (0xD5046093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xcf04s_vo20.bsd
Device Id: 00100100000000000001000010010011 (0x24001093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc6slx9_tqg144.bsd
jtag> print
No. Manufacturer Part Stepping Instruction Register
-------------------------------------------------------------------------------------------------------------------
2 XC6SLX9_TQG144 BYPASS BYPASS
The ‘detect’ command in UrJTAG takes about 0.6 seconds to complete, as shown in the two screenshots of Saleae Logic below.
The CPLD on the ExpressCard is not known by UrJTAG. The BSDL file from the Xilinx Webpack needs to be converted and placed in the BSDL path of UrJTAG.
bsdl2jtag /opt/Xilinx/13.4/ISE_DS/ISE/xbr/data/xc2c384_tq144.bsd xc2c384_tq144
The FT2232H can be manually controlled with a simple C-program and the libftdi and libusbx libraries. A post on the element14 Community site describes how to compile the libraries and examples with gcc. A summary is given below:
confuse-2.7: ./configure; make; make install
libusbx-1.0.17: ./configure --disable-udev; make; make install
libftdi1-1.0: copy ftdi_versio_i.h.in to ftdi_versio_i.h and replace the variables marked with ‘@’ to:
#define FTDI_MAJOR_VERSION 1
#define FTDI_MINOR_VERSION 1
#define FTDI_MICRO_VERSION 0
const char FTDI_VERSION_STRING[] = "1-1.0";
const char FTDI_SNAPSHOT_VERSION[] = "0";
Compile and install the libftdi library as follows:
gcc -c ftdi.c -I/usr/local/include/libusb-1.0
gcc -c ftdi_stream.c -I/usr/local/include/libusb-1.0
ar rs libftdi.a ftdi.o ftdi_stream.o
cp libftdi.a /usr/local/lib/.
cp ftdi.h /usr/local/include/.
The file ftdi_eeprom_version.h needs to be created to compile this part.
#define EEPROM_MAJOR_VERSION 1
#define EEPROM_MINOR_VERSION 1
#define EEPROM_VERSION_STRING "1-1.0"
The ftdi_eeprom program is compiled and installed with
gcc main.c -I/usr/local/include/libusb-1.0 -I/usr/local/include -I. -L/usr/local/lib -lftdi -lusb-1.0 -lconfuse -o ftdi_eeprom
cp ftdi_eeprom /usr/bin
After successful installation of the libraries, the examples (or modified/new code) can be compiled:
gcc simple.c -I/usr/local/include/libusb-1.0 -I/usr/local/include -L/usr/local/lib -lftdi -lusb-1.0 -o ftdi_simple
The bitstream file created by Xilinx ISE can be programmed in the FPGA (or CPLD) using UrJTAG and a Serial Vector Format (SVF) file. This file can be created by Xilinx Impact using the following commands, which can be placed in a script file e.g. ‘bit2svf.impact’:
setMode -bscan
setCable -p svf -file main.svf
addDevice -p 1 -file main.bit
erase -p 1
program -p 1
quit
The command below calls impact with the batch script to create the SVF file.
source /opt/Xilinx/13.4/ISE_DS/settings64.sh /opt/Xilinx/13.4/ISE_DS/
impact -batch bit2svf.impact
Next, the SVF file is used in UrJTAG to program the FPGA.
jtag> bsdl path /home/radko/Projects/documents/ExpressCard_v1.0/bsdl
jtag> cable ft2232 vid=0x0403 pid=0x6010 interface=1
Connected to libftd2xx driver.
jtag> detect
IR length: 22
Chain length: 3
Device Id: 00010110110101011100000010010011 (0x16D5C093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc2c384_tq144.bsd
Device Id: 11010101000001000110000010010011 (0xD5046093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xcf04s_vo20.bsd
Device Id: 00100100000000000001000010010011 (0x24001093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc6slx9_tqg144.bsd
jtag> svf /home/radko/Projects/code/ExpressCard_v1.0_test_FPGA/main.svf progress
detail: Parsing 5660/5664 ( 99%)detail:
detail: Scanned device output matched expected TDO values.
jtag> quit
Similar, the FPGA bitstream file can be saved in impact (as MCS file) for programming in the serial PROM. The SVF file can be created by Xilinx Impact using the following commands, which can be placed in a script file e.g. ‘mcs2svf.impact’:
setMode -bscan
setCable -p svf -file main_flash.svf
addDevice -p 1 -sprom xcf04s -file main_flash.mcs
erase -p 1
program -loadfpga -p 1
quit
Unfortunately, programming multiple devices in a JTAG chain with a SVF file created by Xilinx Impact gives errors in UrJTAG and does not seem to be fully implemented. The solution seems to be to create SVF files with only one device defined as part of the JTAG chain and activate the correct device with the part command.
jtag> bsdl path /home/radko/Projects/documents/ExpressCard_v1.0/bsdl
jtag> cable ft2232 vid=0x0403 pid=0x6010 interface=1
Connected to libftdi driver.
jtag> detect
IR length: 22
Chain length: 3
Device Id: 00010110110101011100000010010011 (0x16D5C093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc2c384_tq144.bsd
Device Id: 11010101000001000110000010010011 (0xD5046093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xcf04s_vo20.bsd
Device Id: 00100100000000000001000010010011 (0x24001093)
Filename: /home/radko/Projects/documents/ExpressCard_v1.0/bsdl/xc6slx9_tqg144.bsd
jtag> part 1
jtag> print
No. Manufacturer Part Stepping Instruction Register
-------------------------------------------------------------------------------------------------------------------
1 XCF04S_VO20 BYPASS BYPASS
jtag> svf /home/radko/Projects/code/ExpressCard_v1.0_test_FPGA/main_flash.svf progress
detail: Parsing 16130/16138 ( 99%)detail:
detail: Scanned device output matched expected TDO values.
jtag> quit
The protocol synchronous serial engine (MPSSE) in the FTDI FT2232H can be used for I2C communication with the Texas Instruments CDCE913 clock synthesizer. The FPGA is programmed to forward the I2C clock (SCL) signal and the bi-directional data (SDA) signal. A state machine programmed in VHDL is used to follow the communication with the CDCE913, which is needed to keep track of the direction of SDA.
The software TI Clock Pro can be used to evaluate configurations and obtain the required register settings. However, the software was found not to work well with the FT2232H interface to the CDCE913. A small C program to read/write bytes over I2C, using the FTDI libMPSSE-I2C library as front-end for the FTDI D2XX driver, was found to miss the acknowledge bit of the slave address byte after the restart. This must have been caused by a bug in the FTDI software, as a datalogger showed an ACK to be forwarded by the FPGA to the FT2232H.
A fully functional I2C communication line was finally obtained with the open source libmpsse-1.3 library and the libftdi driver. A small Python program enables reading and writing bytes through the FPGA to/from the registers of the CDCE913. The first output of the CDCE913 is used to access the 27 MHz clock of the crystal oscillator, which seems to feature quite some jitter. The PLL is configured to provide a 50 MHz and 100 Mhz clock on the two other outputs of the CDCE913. The measurements below have been taken with a 10x probe.
