1. Design

The FPGA and CPLD barely fit side-by-side on the available space of the ExpressCard/54. The FT2232HL is placed as close as possible to the header, to prevent having to route the USB lines across the board. Most components are placed on the front side of the PCB. Only a handful of small capacitors and resistors had to be positioned on the rear side.



The thickness of the PCB inside an ExpressCard/54 enclosure should be as thin as 0.6 mm. It was not possible to limit the routing of wires to the front and rear side. The dense pins of the FPGA and CPLD packages make it impossible to work around a four layer PCB. Unfortunately, most PCB manufacturers do not offer four layer PCBs with a total thickness of just 0.6 mm. The 1.55 mm thick PCB of the first prototype will propably give some problems to fit the board inside the ExpressCard/54 enclosure.


The JTAG signal names on the pins of the FT2232H are with respect to the JTAG chain. The TDI pin is the input for the first device in the JTAG chain. The MPSSE DO signal will connect to TDI to send signals to the JTAG chain. The TDO pin is the output from the last device in the JTAG chain and will connect to the MPSSE DI signal.