The Digilent Inc. “Embedded Linux® Hands-on Tutorial for the ZYBO” is available from the Digilent website in PDF format (revision July 17, 2014). Another version of the tutorial is available on instructables.com. The tutorial attempts to get you through quite some steps. A little extra help is sometimes needed to have success. This post will document my findings for future use.
The notes below have been made while going through the tutorial with Xilinx Vivado 2014.4 on an Ubuntu 14.10 64-bit install. The Xilinx SDK is required as part of the Vivado package. Note that both Vivado and the SDK have dedicated settings files (e.g. settings64.sh), which need to be sourced both to set the required environment variables.
The mkimage tool will be used to create a u-boot image:
sudo apt-get install u-boot-tools
Download the following Digilent packages using git:
git clone -b master-next https://github.com/DigilentInc/u-boot-Digilent-Dev.git
git clone -b master-next https://github.com/DigilentInc/Linux-Digilent-Dev.git
Section 1.2 step 2
Upon opening the design, select to upgrade the design automatically to the current version of Vivado.
Section 1.2 step 5
Select to create a new AXI4 peripheral in the wizard.
Section 1.2 step 7
Do not use space characters in the path of your project folder or Vivado will fail to create the new peripheral IP. The edit_myLed_v1_0 project will not be opened.
Section 1.2 step 9
Add the following two lines of code to myLed_v1_0_S_AVI.v
output wire [3 : 0] led,
assign led = slv_reg0[3:0];
Section 1.2 step 10
Add the following two lines of code to myLed_v1_0.v
output [3 : 0] led,
Section 1.2 step 11
The labels have been updated slightly in the latest version of Vivado. Close the project when the new IP is packaged.
Section 1.2 step 13
The “Run Connection Automation” banner does not show up in the top of the screen after adding the new peripheral IP to the design. The three inputs can be connected manually. The S_AXI input is connected to M00_AXI output of the processing_system7_0_axi_periph block. The clock (s_axi_aclk) and reset (s_axi_aresetn) signals are connected to the nets used by the other peripheral IP blocks.
Section 1.2 step 16
Before generating a bitstream, open the address editor and run Auto Assign Address from the context menu on the Unmapped Slave myLed_0.
Section 2.2 step 2
Compile u-boot with the following commands:
make CROSS_COMPILE=arm-xilinx-linux-gnueabi- zynq_zybo_config
Section 3.2 step 1
After completion of system synthesis and generation of the bitstream, the hardware design is exported (to the SDK). Export to the local project and include the bitstream. Next, select Launch SDK from the File menu.
Section 3.2 step 5
The name of the target platform is system_wrapper_hw_platform_0.
Section 3.2 step 10
Set the output BIF file path to: zybo_base_system/sd_image/output.bif
First add the file zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.sdk/FSBL/Debug/FSBL.elf as bootloader to the list of boot image partitions. Secondly, add the file zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.sdk/system_wrapper_hw_platform_0/system_wrapper.bit as datafile. The third and last file to add is the datafile zybo_base_system/sd_image/u-boot.elf. The output path is set to zybo_base_system/sd_image/BOOT.bin.
Configure and compile the linux kernel with the following commands:
make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig
make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi-
make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- UIMAGE_LOADADDR=0x8000 uImage
Section 5.2 step 1
The device tree source file to be modified is Linux-Digilent-Dev/arch/arm/boot/dts/zynq-zybo.dts.
The file ramdisk8M.image.gz should be obtained from the ZYBO Linux Reference Design. However, this does not appear to have been released yet by Digilent. The file in a reference design for a similar board can be used unstead: ZedBoard_OOB_Design.zip.
An empty ramdisk can be created with the following commands. It will have to be populated with a root filesystem though in order to work. Some basic instructions on Zynq root filesystem creation can be found online.
dd if=/dev/zero of=ramdisk8M.image bs=1024 count=8192
mke2fs -F ramdisk8M.image -L "ramdisk" -b 1024 -m 0
tune2fs ramdisk8M.image -i 0
chmod 777 ramdisk8M.image
gzip -9 ramdisk8M.image
mkimage -A arm -T ramdisk -c gzip -d ./ramdisk8M.image.gz uramdisk.image.gz
Change the device tree source file Linux-Digilent-Dev/arch/arm/boot/dts/zynq-zybo.dts to the following bootargs:
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
Section 5.2 step 3
The filename of one of the files to be copied to the SD card is BOOT.bin.
Section 5.2 step 4
Connect the serial port terminal (GtkTerm) to /dev/ttyUSB1 after power up of the ZYBO board.
Section 6.2 step 3
The source code for the driver myled.c can be downloaded from the version of the tutorial on instructables.com. One additional header file needs to be included to successfully compile the new driver:
Remember to set the environment variables of the Xilinx SDK before compiling the new driver.